Arteris (NASDAQ:AIP) executives highlighted the company’s focus on on-chip and chiplet data movement, recent product launches, and an expanding security verification offering during a presentation at the 28th Annual NEDM Growth Conference. CEO Charlie Janac and CFO Nick Hawkins also discussed the company’s deferred revenue model, backlog trends, and expectations around free cash flow and profitability.
Positioning as a “data movement” semiconductor IP provider
Janac described Arteris as a semiconductor IP company focused on technology that moves data inside a chip, between chiplets, and in some applications between chips. He framed modern SoCs at a high level as performing three roles—processing data, storing data, and moving data—and said Arteris concentrates on the data movement function.
Software and connectivity tools, plus security verification via acquisition
Janac noted that Arteris acquired Magillem in 2020. He said Magillem addresses SoC connectivity definition, register management and hardware-software integration, and IP block packaging—tasks he said were historically managed with spreadsheets that no longer scale as chip connections increase.
He also discussed Arteris’ latest acquisition: Cycuity, a hardware security verification company. Janac said Arteris intends to keep Cycuity open to any IP block requiring security verification, while also pursuing security for data flowing through Arteris’ NoC IP. He characterized the combination as supporting both functional safety and secure data movement.
Product roadmap emphasizes automation and chiplets
Janac said Arteris targets at least two enhancement releases for existing products each year and aims to deliver one new product annually. He highlighted FlexGen, which the company began shipping in February 2025. FlexGen is designed to automatically generate NoC IP based on a connection list, IP block exit port locations, and a floor plan, with users specifying performance objectives to produce a NoC implementation.
Janac said customers can build NoCs roughly 10 times faster with FlexGen compared to manual flows with expert users, and he said customers can typically achieve up to 30% shorter “Y length” in designs when chips are complex enough.
Looking ahead, Janac said Arteris plans to deliver a chiplet solution by the end of the first quarter of 2026, following a June 2025 announcement. He described this as supporting cache-coherent heterogeneous chiplets, enabling coherent reads and writes across multiple dies—up to four—so software can be programmed as though it is operating on a single memory space or processor.
Markets: AI, automotive, RISC-V, and standards support
Janac said growing chip complexity—more processors, more IP blocks, increased use of chiplets, and AI workloads that require moving large quantities of parameters—has elevated the importance of data movement. He said Arteris has been pushing into AI-related designs, noting that about half of the company’s design starts are typically for AI applications across training, data center inference, and edge inference.
He also said the company supports both ARM and RISC-V processor ecosystems. Janac cited recent publicly announced relationships, including AMD (announced in the second quarter) and Altera (announced in the third quarter). He also pointed to work with NanoXplore for satellite SoCs and with 2V Systems for a cache-coherent I/O hub chiplet, describing it as a “traffic cop” for chiplets.
On industry standards, Janac said Arteris joined the AMD-led Ultra Accelerator Link Consortium and plans to support the UALink protocol.
Financial model: RPO growth, deferred revenue, and free cash flow
Hawkins described the company’s deferred revenue model and explained why profitability can lag free cash flow. He said customers tend to pay upfront, with deal value initially recorded on the balance sheet in remaining performance obligations (RPO). He characterized the income statement impact as having an 18-month to two-year delay due to revenue recognition, which can lead to negative profitability while free cash flow remains positive.
Discussing results through the third quarter (noting the company had not yet reported fourth quarter results at the time), Hawkins said the quarter featured strong performance that met or beat guidance, including top-line measures above the top end of guidance in some cases. He emphasized that free cash flow was positive even while profitability was negative.
Key metrics Hawkins cited included:
- RPO near $105 million at the end of the third quarter, which he said was about 1.5x annual GAAP revenue run rate and up 34% year over year.
- Annual contract value (ACV) plus trailing royalties up 24%, with revenue up 18%, which he said reflects the lagging effect of deferred revenue.
Hawkins also discussed the company’s royalty profile. He said about one-fifth of the design pipeline is generating most current royalties, while a larger set of pre-mass production programs have not yet contributed royalty payments. He said a little over half of Arteris’ total royalty stream comes from automotive, describing the segment as a “sweet spot” where high volume meets high royalty rate.
He contrasted the company’s current royalty diversification with earlier concentration, noting that HiSilicon once represented 90% of the royalty stream before a U.S. government ban led that stream to evaporate. Hawkins said Arteris has since eclipsed prior royalty levels and now has five customers sending six-figure royalty checks each quarter, with expectations that additional customers would enter that group.
On guidance as of the third quarter, Hawkins said the company was looking at revenue “around the $69 million mark,” free cash flow averaging approximately plus $4 million, and non-GAAP operating income (NGOI) of negative $13 million. Janac added that Arteris had promised Wall Street it would be free cash flow positive in 2025 and said the company has achieved that, also noting a strong balance sheet without debt.
About Arteris (NASDAQ:AIP)
Arteris, Inc is a fabless semiconductor intellectual property (IP) company specializing in on-chip interconnect solutions and system IP for advanced integrated circuits. The company’s core products include its FlexNoC network-on-chip (NoC) fabrics, Ncore cache coherent interconnect IP, and CodaCache memory subsystem IP. These technologies enable semiconductor and systems companies to design scalable, energy-efficient chips for applications ranging from automotive and artificial intelligence (AI) to 5G communications and high-performance computing.
Founded in 2003 and headquartered in Santa Clara, California, Arteris serves a global customer base across North America, Europe, and Asia.
